SHAKE-256: a RISC-V ISA extension for SLH-DSA
320-bit SIMD instructions on CV32E40P that swallow the Keccak hot path of post-quantum signatures, validated on a PYNQ-Z2.
Putting cryptography into silicon, and writing about it afterwards.
Computer Science at National Cheng Kung University. I spend most of my time on the hardware side: RISC-V ISA extensions, FPGA bring-up, and accelerating post-quantum signatures. The rest goes into hackathons, and into writing down what broke.

320-bit SIMD instructions on CV32E40P that swallow the Keccak hot path of post-quantum signatures, validated on a PYNQ-Z2.
test
Turning the convex traffic mirrors nobody maintains into a ranked, dispatchable inventory, using street-view imagery and open accident data.
Built for the CMoney × AWS AI Hackathon — turning a portfolio tracker from a bookkeeping form into something that speaks first.
Theme "Agent × Smart City". We converged on road convex mirrors — a maintenance pipeline, oncoming-vehicle warning at unsignalised intersections, and mirrors doubling as road-condition sensing nodes.
Role Concept, system designTeam Team of fourStack Google Cloud · AI Agent · Computer Vision
Chose a problem at the intersection of security and finance, building on my coursework in international financial markets and international security.
Role Proposal, developmentStack Web · LLM · Security
Entered with my capstone work — the SHAKE-256 RISC-V ISA extension for SLH-DSA.
Role FPGA integration and hardware testingStack RISC-V · Verilog · FPGA · Post-quantum crypto
Research collaboration, hackathon teams, or just wanting to talk about RISC-V and post-quantum crypto — email is best.